A packaging technique called a wafer level (Wafer Level) CSP, that is, a system of integrating a packaging process which is an assembly step with a wafer process which mainly uses photolithography, and completing a packaging step at a wafer level has an advantage of drastically reducing the number of steps compared with the conventional method in which each chip is subjected to a packaging process after cut out from the wafer, because in the wafer level CSP, the packaging process is conducted by making use of the wafer process. The wafer level CSP is also called wafer process•package (WPP).
The above-described wafer level CSP is expected to actualize a reduction in the manufacturing cost of the CSP together with a reduction in the number of steps, because as compared, for example, with a CSP having a structure in which a tape-shaped interconnect having a copper (Cu) interconnect formed over an insulating tape is adhered onto the main surface of the semiconductor chip, an interconnect layer (tape-shaped interconnect) inside of the former CSP, which is called “interposer”, for converting the pitch of a bonding pad to the pitch of a solder bump can be replaced with a relocating wiring layer formed over the wafer.
A description on the wafer level CSP can be found in, for example, pages 81 to 113, Electronics Jisso Gijutsu: 2000, Extra Number (published by Gicho Publishing and Advertising Co., Ltd., on May 28, 2000), or International Laid-Open No. WO/23696.
In the conventional method of subjecting every chip cut out from a wafer to a packaging process (post-step), an operation mode such as word constitution or bit constitution was changed (design was switched) by bonding option, for example, in memory LSI such as DRAM (Dynamic Random Access Memory) in order to meet the request of users promptly. Such a technique of changing electrical characteristics, that is, carrying out bonding option after dividing into individual chips is described in Japanese Unexamined Patent Publication No. Hei 11 (1999)-40563 or Hei 7 (1995)-161761.
In Japanese Unexamined Patent Publication No. Hei 11 (1999)-40563, disclosed are: (1) a method of connecting, in advance, two interconnects having different electrical characteristics to a bonding pad (semiconductor element electrode disposed on a semiconductor chip) to be connected to a bonding wire, tape lead or external connection ball and cutting by laser one of these interconnects in accordance with the electrical characteristics requested; (2) a method of changing the wiring of a bonding wire which connects a semiconductor element electrode (bonding pad) disposed on the semiconductor chip to the electrode portion of a semiconductor package; and (3) a method of changing the disposal position of an external connection ball to be connected to the electrode (bonding pad) of a semiconductor chip in a CSP.
In Japanese Unexamined Patent Publication No. Hei 7 (1995)-161761, described is a method of forming, in a semiconductor device in which bonding pads on the semiconductor element surface and a plurality of leads are connected via a bonding wire, plural rows of pad groups, each having a row of a plurality of bonding pads equal in function, at the central part of the semiconductor device while classifying the groups by function, and changing the bonding pad to which a bonding wire is connected, thereby altering the combination of connection between the lead and bonding pad, depending on the design.